Image processor and image processing method

ABSTRACT

An object of the present invention is to provide an image processing apparatus in which a delay from start of image data input to start of coding is small, the capacity of a temporary storage device used for temporarily storing the image data to be coded is small, and the possibility of discarding the image data is low even when coding is delayed and, therefore, the image quality is hardly degraded. Since this apparatus is provided with a flag generator for generating control information according to the processing status, input/output of the image data in/from the temporary storage device is performed for each unit amount, and storage and coding of the image data are executed according to the control information.

TECHNICAL FIELD

The present invention relates to an image processing apparatus and animage processing method and, more particularly, to image processing inwhich input image data is temporarily stored in a storage device, andthe stored image data is subjected to coding.

BACKGROUND ART

Although image data including a time-varying image is originally analogdata, when this data is digitized, various kinds of complicated signalprocessing and data compression can be performed on the data and,therefore, the technology of image digitization forms an importantfield. In an image processing apparatus according to a prior art, inputanalog image data is subjected to analog-to-digital conversion andcompressive coding for recording or transmission, and generally thedigitized image data is temporarily stored in a high-speed storage unitsuch as a memory before being subjected to compressive coding. Anexample of an image processing apparatus with such temporary storage isdisclosed in Japanese Patent Application No. Hei. 7-273461, in whichdigital image data is temporarily stored in a memory called an imageframe memory.

FIG. 10 is a block diagram showing the structure of an image processingapparatus according to the prior art. As shown in the figure, the priorart image processing apparatus is provided with an A/D converter 1001,an image input controller 1002, a memory controller 1003, an encoder1004, an input image memory 1005, and a rate buffer 1006, and thisapparatus receives an analog video signal S1051 and outputs coded dataS1057. In FIG. 10, signals shown by solid lines indicate the flow ofdata to be processed, and signals shown by broken lines indicate theflow of signals for control.

The A/D converter 1001 subjects the input analog video signal S1051 toanalog/digital conversion to generate digital image data S1052. Theimage input controller 1002 generates an image input enabling signalS1061 indicating whether the input digital image data S1052 is“effective” or “ineffective”. The memory controller 1003 controlsstorage and readout of the digital image data into/from the memory. Theencoder 1004 subjects the digital image data S1055 to a predeterminedcompressive coding process to generate coded data S1056.

The input image memory 1005 temporarily stores the digital image dataS1054 for the work of the compressive coding process. In the prior artimage processing apparatus, the input image memory is divided intoplural regions each region storing a predetermined quantity of digitalimage data. Here, the input image memory 1005 has two regions, namely, afirst region 1005 a and a second region 1005 b, each region being ableto store one frame (one screen) of digital image data.

The rate buffer 1006 temporarily stores the coded data S1056 generatedby the coder 1004 and outputs the data so that the output S1057 from theimage processing apparatus is output at a constant rate. Hereinafter,the operation of the prior art image processing apparatus so constructedwill be described.

When an analog video signal S1051 is input to the image processingapparatus, the analog video signal S1051 is input to the A/D converter1001, wherein it is subjected to analog/digital conversion. The A/Dconverter 1001 generates digital image data S1052 and outputs this datato the image input controller 1002. The input analog video signal S1051includes a signal of an effective region corresponding to a portion ofimage to be displayed, and a signal of an ineffective region other thanthe effective region. The image input controller 1002 generates an imageinput enabling signal S1061 indicating whether the input digital imagedata S1052 is “effective” or “ineffective”, and outputs both of thedigital image data S1053 and the image input enabling signal S1061 tothe memory controller 1003.

The memory controller 1003 stores the digital image data S1053 in theinput image memory 1005, according to the image input enabling signalS1061 supplied from the image input controller 1002 and an image inputrequest signal S1063 supplied from the encoder 1004 which is describedlater. When the encoder 1004 goes into the coding executable state andoutputs an image input request signal S1063 indicating a request fordigital image data to be subjected to coding, to the memory controller1003, the memory controller 1003 stores the digital image data S1053 inthe first region 1005 a of the input image memory according to the imageinput enabling signal S1061 indicating that the digital image data S1053is effective.

When a predetermined amount of the digital image data S1053 is stored inthe first region 1005a, the memory controller 1003 generates a codingstart signal S1062 and outputs it to the encoder 1004 so that theencoder 1004 starts coding. Here, the memory controller 1003 generatesthe signal when one frame of digital image data has been stored.

The encoder 1004 does not perform coding until it receives the codingstart signal S1062 directing coding, from the memory controller 1003.When the encoder 1004 has received this signal, it receives the digitalimage data S1055 stored in the first region 1005 a through the memorycontroller 1003, and performs coding of this data. This coding iscarried out according to a predetermined scheme. For example, one frameof digital image data is divided into plural blocks each having apredetermined size, and coding is carried out block by block. When thiscoding is carried out, the size of each block is generally 8×8 pixels or16×16 pixels. Further, “a pixel” is discrete unit data as a component ofdigital image data, and it has a pixel value showing the brightness orcolor of the image.

The encoder 1004 outputs coded data S1056 generated by the coding, tothe rate buffer 1006. The coded data S1056, which has temporarily beenstored in the rate buffer 1006, is output to the outside of the imageprocessing apparatus as an output S1057 from the apparatus, fortransmission or the like. On the other hand, as the coding is executed,the encoder 1004 generates an image input request signal S1063indicating that one frame of digital image data to be coded next is tobe input, and outputs this signal S1063 to the memory controller 1003.

In the memory controller 1003, the digital image data S1053 is stored inthe input image memory 1005 according to the image input request signalS1063 and the input enabling signal S1061 indicating that the digitalimage data S1053 is effective. As described above, one frame of digitalimage data is stored in the memory 1005. However, at this time, thememory controller 1003 stores the data in the second region 1005 bdifferent from the first region 1005 a.

When one frame of digital image data S1053 (a unit of digital imagedata) has been stored in the second region 1005 b, the memory controller1003 generates a coding start signal S1062 indicating that coding shouldbe started, and outputs this signal to the encoder 1004. If the encoder1004 has ended coding of the previous one frame of digital image data(data which were stored in the region 1005 a) when it receives thecoding start signal S1062 which directs the encoder to start coding,from the memory controller 1003, the encoder 1004 receives the digitalimage data S1055 stored in the second region 1005 b through the memorycontroller 1003, performs coding of this data, and outputs coded data tothe rate buffer 1006.

As described above, in the prior art image processing apparatus, digitalimage data is stored alternately in the first region 1005 a and thesecond region 1005 b possessed by the input image memory 1005, and thestored data is read alternately from these regions to be coded by theencoder 1004.

FIG. 11 is a timing chart showing the processing status in the normalstate wherein the above-mentioned processing is carried out normally. InFIG. 11, “image input request signal S1063” indicates the state of thesignal S1063 output from the encoder 1004 to the memory controller 1003,and its Hi state shows that the encoder 1004 requests digital imagedata. Further, “image input enabling signal S1061” indicates the stateof the signal S1061 which is generated by the image input controller1002 to be output to the memory controller 1003, and its Hi state showsthat the digital image data is effective and to be stored in the memory.

Furthermore, “storage of image data” in FIG. 11 indicates regions of theinput image memory 1005 where the digital image data S1054 is stored. Asdescribed above, under control of the memory controller 1003, thedigital image data is stored alternately in the first region 1005 a (inthe figure, memory (1)) and the second region 1005 b (in the figure,memory (2) ), which regions are possessed by the input image memory1005.

Turning to FIG. 11, “coding start signal S1062” indicates the state ofthe signal S1062 output from the memory controller 1003 to the encoder1004, and its Hi state shows that coding should be started. Further,“coding process” indicates a coding process performed by the encoder1004, and it indicates that the digital image data stored in the firstregion 1005 a (in the figure, memory (1)) or the second region 1005 b(in the figure, memory (2)) is being subjected to coding, which regionsare possessed by the input image memory 1005.

As shown in the figure, in accordance with the Hi state of the imageinput request signal S1063, from timing t110, the digital image datawhose image input enabling signal S1061 is in the Hi state is stored inthe first region, as shown by “image data storage”. Then, in accordancewith the Hi state of the coding start signal S1062 shown in the figure,from timing t111, the digital image data is read from the first regionto be coded. Further, as the coding is carried out, storage of data inthe second region is carried out as shown by “image data storage”.Likewise, from timing t112, storage of data in the first region andreadout of data from the second region are carried out. As shown by“image data storage” and “coding process” in the figure, at the timingwhen storage of data in one of the regions is carried out, readout ofdata from the other region is carried out.

On the other hand, FIG. 12 is a timing chart showing the processingstate where an error has occurred for some reason, and this errordisables the normal processing shown in FIG. 11. Also in this case, theprocessing is carried out in like manner as shown in FIG. 11 untiltiming t120.

In FIG. 12, “coding process” indicates that the coding of the digitalimage data stored in the second region 1005 b (FIG. 1), which coding hasbeen performed from timing t120, takes time and, therefore, the end ofthis coding is delayed to timing t121. Accordingly, with respect to thesecond region 1005 b of the input image memory 1005, readout of thedigital image data from this region is carried out until reaching timingt121, and thereby storage of digital image data into the second regionshown by “image data storage” is not performed although this storageought to be carried out if the processing has been normally carried out.Therefore, as shown by the broken-line square of “image data storage” inFIG. 12, the digital image data which has not been stored is discarded,i.e., it is not subjected to the coding process.

After the coding process has ended at timing t122, the normal processingis carried out again. As described above, in the prior art imageprocessing apparatus, storage and readout are alternately performedin/from the regions possessed by the input image memory 1005. In thisway, the prior art image processing apparatus is able to perform storageand coding of digital image data at their respective timings, and copeswith a delay or the like in the coding process by discarding the digitalimage data. Also in the apparatus disclosed in the above-mentionedJapanese Patent Application No. 7-273461, memory management similar tothat mentioned above is performed.

However, the conventional image processing apparatus has the followingproblems.

First of all, when the image processing apparatus is used in a visualtelephone system or as a monitor between an input apparatus such as avideo camera and an output apparatus such as a display, it is requiredto have the property of operating real-time. When the apparatus isapplied to such use, the apparatus captures an image from a video cameraor the like as a target to be processed and, after processing, codeddata is output from the apparatus for transmission or the like. At thereproduction end, the coded data is subjected to decoding and thenoutput as an image. So, if a delay from inputting analog image data todisplaying output image data is considerable, a time difference occursin motions between the real image taken by the camera and the displayedimage, resulting in unnatural image display.

As described above, in the prior art image processing apparatus, inorder to control data input/output to/from the input image memory, theencoder 1004 starts coding in response to the coding start signal S1062when the digital image data to be subjected to coding has been stored bya predetermined amount (in the above example, one frame) (FIG. 11).Therefore, in the prior art image processing apparatus, because of adelay between the signal input and the start of coding, it is hard tosatisfactorily display the image when the apparatus is applied to suchuse. This is the first problem.

Further, in the prior art image processing apparatus, as describedabove, unconditional discarding of digital image data is performed forerror processing. Since this unconditional discarding causes absence ofdata, frequent delays in the coding process result in degradation ofimage quality. This is the second problem.

Moreover, since the input image memory 1005 is divided into the regionwhere storage is performed and the region where readout is performed,when the amount of digital image data to be processed is large, thememory capacity must be increased according to the data amount. However,to require a bulk memory results in an increase in the cost and,therefore, it is difficult to fabricate an inexpensive apparatus forpropagation. This is the third problem.

SUMMARY OF THE INVENTION

The present invention is made in view of the above-describedcircumstances and has an object to provide an image processing apparatuswhich reduces a delay time from start of signal input to start of codingand, therefore, is suitable for the real-time use.

Further, the present invention has another object to provide an imageprocessing apparatus which reduces the amount of data to be discardedand thereby improves the image quality, even when a delay or the likeoccurs during coding.

Further, the present invention has still another object to provide animage processing apparatus which reduces the capacity of memory requiredfor temporary storage of digital data and thereby reduces the cost.

Further, the present invention has yet another object to provide animage processing method which reduces a delay time before start ofcoding, an image processing method which reduces the possibility ofdiscarding data even if coding is delayed, and an image processingmethod which reduces the capacity of memory required for temporarystorage of data.

To attain the above-mentioned objects, an image processing apparatus ofa first aspect of the present invention, which is an apparatus forstoring input image data in a temporary storage device and subjectingthe stored image data to a coding process, comprises: an image inputcontrol device for controlling storage of the input image data in thetemporary storage device; a storage control device for executing storageof the image data in the temporary storage device under control of theimage input control device and, when a predetermined unit storage amountof data has been stored, generating storage information indicating this;a coding device for reading the image data stored in the temporarystorage device to subject the read data to a predetermined codingprocess and, when a predetermined unit processing amount of data hasbeen subjected to the coding process, generating process informationindicating this; and a control information generating device forgenerating first control information used by the image input controldevice to control the storage, and second control information used bythe coding device to control the coding process, in accordance with thestorage information generated by the storage control device and theprocess information generated by the coding device. Thereby, the controlinformation generating device generates control information forcontrolling the storage and the coding process, according to the imageprocessing status obtained from the storage information and the processinformation.

According to an image processing apparatus of another aspect of thisinvention, the control information generating device generates, as thefirst control information, storage stop information indicating that thestorage of the input image data should be stopped, and generates, as thesecond control information, coding stop information indicating that thecoding process should be stopped. According to the status of imageprocessing, the storage is stopped to protect the data which havealready been stored, and the coding is stopped to stand by until data tobe coded are stored.

According to an image processing apparatus another aspect of thisinvention, the control information generating device generates, as thefirst control information, storage stop information indicating that thestorage of the input image data should be stopped, and generates, as thesecond control information, continuous process information indicatinghow many times the coding device can continuously perform the codingprocess on the unit processing amount of image data. According to thestatus of image processing, the storage is stopped to protect the datawhich have already been stored, and continuous coding according to thestatus of storage is performed.

According to an image processing apparatus of another aspect of thisinvention, the control information generating device comprises: astorage information counting device for counting the storage informationand holding the result as a storage information count value; a processinformation counting device for counting the process information andholding the result of the count as a process information count value; anaddition control device for outputting an addition enabling signal whenthe count of the storage information is performed by a predeterminednumber of times, and outputting an addition disabling signal when thecount of the process information is performed by a predetermined numberof times; a storage information count value change device for adding apredetermined value to the storage information count value according tothe addition enabling signal or the addition disabling signal, therebygenerating a storage information count value after processing; a codableunit number generating device for subtracting the process informationcount value from the storage information count value after processing,thereby generating a codable unit number; a first control informationgenerating device for comparing the codable unit number with a firstpredetermined value and, when these values match, generating the firstcontrol information; and a second control information generating devicefor comparing the codable unit number with a second predetermined valueand, when these values match, generating the second control information.Thereby, the codable unit number indicating the storage status of datato be coded is obtained from the storage information and the processinformation, and the control information is generated according to thecodable unit number to control the storage and the coding.

According to an image processing apparatus of another aspect of thisinvention, the control information generating device comprises: astorage information counting device for counting the storage informationand holding the result as a storage information count value; a processinformation counting device for counting the process information andholding the result as a process information count value; an additioncontrol device for outputting an addition enabling signal when the countof the storage information has been performed by a predetermined numberof times, and outputting an addition disabling signal when the count ofthe process information has been performed by a predetermined number oftimes; a storage information count value change device for adding apredetermined value to the storage information count value according tothe addition enabling signal or the addition disabling signal, therebygenerating a storage information count value after processing; a codableunit number generating device for subtracting the process informationcount value from the storage information count value after processing,thereby generating a codable unit number; and a first controlinformation generating device for comparing the codable unit number witha first predetermined value and, when these values match, generating thefirst control information; wherein the codable unit number is used asthe second control information. Thereby, the codable unit numberindicating the storage status of data to be coded is obtained from thestorage information and the process information, and the controlinformation is generated according to the codable unit number to controlthe storage and the continuous coding.

An image processing method according to another aspect of thisinvention, which is a method for storing input image data in a temporarystorage device and performing coding of the stored image data,comprises: controlling storage of the input image data in the temporarystorage device; executing storage of the image data in the temporarystorage device under control of the image input control step and, when apredetermined unit storage amount of data has been stored, generatingstorage information indicating this; reading the image data stored inthe temporary storage device to subject the read data to a predeterminedcoding process and, when a predetermined unit processing amount of datahas been subjected to the coding process, generating process informationindicating this; and generating first control information used in thecontrolling to control the storage, and second control information usedin the coding to control the coding process, according to the storageinformation generated in the storage control and the process informationgenerated in the coding. Thereby, in the control information generating,the control information for controlling the storage and the codingprocess is generated according to the image processing status obtainedfrom the storage information and the process information.

According to an image processing method of another aspect of thisinvention, in the control information generating, storage stopinformation indicating that the storage of the input image data shouldbe stopped is generated as the first control information, and codingstop information indicating that the coding process should be stopped isgenerated as the second control information. According to the status ofimage processing, the storage is stopped to protect the data which havealready been stored, and the coding is stopped to stand by until data tobe coded are stored.

According to an image processing method of another aspect of thisinvention, in the control information generating, storage stopinformation indicating that the storage of the input image data shouldbe stopped is generated as the first control information, and continuousprocess information indicating how many times the coding process on theunit processing amount of image data can be continuously performed inthe coding is generated as the second control information. According tothe status of image processing, the storage is stopped to protect thedata which have already been stored, and continuous coding according tothe status of storage is performed.

According to an image processing method of yet another aspect of thisinvention, the control information generating comprises: counting thestorage information and holding the result as a storage informationcount value; counting the process information and holding the result asa process information count value; outputting an addition enablingsignal when the count of the storage information is performed by apredetermined number of times, and outputting an addition disablingsignal when the count of the process information is performed by apredetermined number of times; adding a predetermined value to thestorage information count value according to the addition enablingsignal or the addition disabling signal, thereby generating a storageinformation count value after processing; subtracting the processinformation count value from the storage information count value afterprocessing, thereby generating a codable unit number; comparing thecodable unit number with a first predetermined value and, when thesevalues match, generating the first control information; and comparingthe codable unit number with a second predetermined value and, whenthese values match, generating the second control information. Thereby,the codable unit number indicating the storage status of data to becoded is obtained from the storage information and the processinformation, and the control information is generated according to thecodable unit number to control the storage and the coding.

According to an image processing method of yet another aspect of thisinvention, the control information generating comprises: counting thestorage information and holding the result as a storage informationcount value; counting the process information and holding the result asa process information count value; outputting an addition enablingsignal when the count of the storage information is performed by apredetermined number of times, and outputting an addition disablingsignal when the count of the process information is performed by apredetermined number of times; adding a predetermined value to thestorage information count value according to the addition enablingsignal or the addition disabling signal, thereby generating a storageinformation count value after processing; subtracting the processinformation count value from the storage information count value afterprocessing, thereby generating a codable unit number; comparing thecodable unit number with a first predetermined value and, when thesevalues match, generating the first control information; and using thecodable unit number as the second control information. Thereby, thecodable unit number indicating the storage status of data to be coded isobtained from the storage information and the process information, andthe control information is generated according to the codable unitnumber to control the storage and the continuous coding.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the structure of an imageprocessing apparatus according to a first embodiment of the presentinvention.

FIG. 2 is a block diagram illustrating the internal structure of a flaggenerator included in the image processing apparatus according to thefirst embodiment.

FIGS. 3(a)-3(c) are diagrams for explaining the structure of digitalimage data to be processed by the image processing apparatus accordingto the first embodiment.

FIGS. 4 and 5 are timing charts for explaining the processing by theimage processing apparatus according to the first embodiment.

FIG. 6 is a block diagram illustrating the structure of an imageprocessing apparatus according to a second embodiment of the presentinvention.

FIG. 7 is a block diagram illustrating the internal structure of a flaggenerator included in the image processing apparatus according to thesecond embodiment.

FIGS. 8 and 9 are timing charts for explaining the processing by theimage processing apparatus according to the second embodiment.

FIG. 10 is a block diagram illustrating the structure of an imageprocessing apparatus according to the prior art.

FIGS. 11 and 12 are timing charts for explaining the processing by theimage processing apparatus according to the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1

An image processing apparatus according to a first embodiment of thepresent invention is provided with a flag generator, and controls imageprocessing and manages a memory by using control flags.

FIG. 1 is a block diagram illustrating the structure of the imageprocessing apparatus according to the first embodiment, which receivesanalog image data and subjects the data to digital conversion andcompressive coding. As shown in the figure, the image processingapparatus according to the first embodiment is provided with an A/Dconverter 101, an image input controller 102, a memory controller 103,an encoder 104, an input image memory 105, a rate buffer 106, and a flaggenerator 107. This apparatus receives an analog video signal S151, andoutputs coded data S157. In FIG. 1, signals shown by solid linesindicate the flow of data to be processed, and signals shown by brokenlines indicate the flow of signals for control.

The A/D converter 101 subjects the input analog video signal S151 toanalog/digital conversion to generate digital image data S152. The imageinput controller 102 generates an image input enabling signal S161indicating whether the input digital image data S152 is “effective” or“ineffective”. In this first embodiment, as in the case of the prior artimage processing apparatus, the image input controller 102 generates animage input enabling signal S161 according to the distinction betweenthe effective region and the ineffective region of the digital imagedata and, further, it refers to an error flag S162 supplied from theflag generator 107 which will be described later. When the error flagS162 is ineffective (Lo state), the image input controller 102 generatesan image input enabling signal S161 indicating “effective”. When theerror flag S162 is effective (Hi state), it generates an image inputenabling signal S161 indicating “ineffective”.

The memory controller 103 controls storage and readout of digital imagedata in/from the memory. The memory controller 103 according to thisfirst embodiment controls storage and readout of digital image datain/from the input image memory 105 for a predetermined amount as a unitand, when storage of data for each unit has been completed, it generatesa writing end signal S164 indicating the completion and then outputsthis signal to the flag generator 107. Therefore, the memory controller103 functions as a storage control device which performs storage ofdigital image data into a temporary storage device (input image memory105) under control of an image input control device (image inputcontroller 102) and generates storage information (writing end signalS164) when a predetermined amount (unit amount) of data has been stored.

The encoder 104 subjects the digital image data S155 to a predeterminedcompressive coding process to generate coded data S156. The encoder 104according to this first embodiment refers to an empty flag S165 which issupplied from the flag generator 107 described later. When the emptyflag S165 is in the Lo state, the encoder 104 performs coding, and whenthe empty flag S165 is in the Hi state, the encoder 104 does not performcoding. Further, the encoder 104 performs coding for a predeterminedamount of data as a unit. When coding for each unit has been completed,it generates a coding end signal S166 indicating the completion andoutputs this signal to the flag generator 107. Accordingly, the encoder104 functions as a coding device which reads image data stored in atemporary storage device (input image memory 105), subjects the data toa prescribed coding process, and generates process information (codingend signal S166) when a predetermined amount (unit amount) of data hasbeen coded.

The input image memory 105 temporarily stores the digital image dataS154 for the work of compressive coding. In this first embodiment, incontrast with the prior art image processing apparatus, the memory 105is not divided into specific regions (two regions in the prior artexample) to be managed, and a capacity enough to store a predeterminedamount (one frame) of digital image data suffices for the input imagememory 105. The rate buffer 106 temporarily stores the coded data S156so that the coded data S157, which is output from the image processingapparatus, is output at a constant rate.

The flag generator 107 counts the writing end signal for each unitamount supplied from the memory controller 103 and the coding end signalfor each unit amount supplied from the encoder 104 and, according to theresult of the count, it generates flags (empty flag and error flag) usedfor controlling input/output of the data to/from the memory. Therefore,the flag generator 107 functions as a control information generatingdevice which generates first control information (error flag) used by animage input control device (image input controller 102) to controlstorage, and second control information (empty flag) used by a codingdevice (encoder 104) to control coding, according to the storageinformation (writing end signal S164) generated by the storage controldevice (memory controller 103) and the process information (coding endsignal S166) generated by the coding device (encoder 104).

FIG. 2 is a block diagram illustrating the internal structure of theflag generator 107 (FIG. 1). As shown in FIG. 2, the flag generator 107is provided with a write block counter 201, a read block counter 202, acarry flag holder 203, a selector 204, an adder 205, a subtracter 206,first and second comparators 207 and 208, an error flag holder 209, andan empty flag holder 210.

The write block counter 201 counts the writing end signal S164 suppliedfrom the memory controller 103 (FIG. 1) for each slice (described later)as a unit, and outputs the count value to the adder 205 while holdingit. This count is carried out according to a tetradecimal number system.When the count value has reached 14 and the next writing end signal S164has been input, the count value becomes 0 and the carry flag holder 203(described later) enters in the set state. Further, when a counter resetsignal S163 a instructing initialization is supplied from the imageinput controller 102 (FIG. 1), the count value becomes 0. Accordingly,the write block counter 201 functions as a storage information countdevice which counts the storage information (writing end signal S164)and holds the result of the count as a storage information count value.

The read block counter 202 counts the coding end signal S166 suppliedfrom the encoder 104 (FIG. 1) for each slice (described later) as aunit, and outputs the count value to the subtracter 206 while holdingit. This count is carried out according to a tetradecimal number system.When the count value has reached 14 and the next coding end signal S166has been input, the count value becomes 0 and the carry flag holder 203described later enters in the reset state. Accordingly, the read blockcounter 202 functions as a process information count device which countsthe process information (coding end signal S166) and holds the result ofthe count as a process information count value.

The carry flag holder 203 is set when the counting operation of thewrite block counter 201 has reached 15, namely, when the count value ofthe write block counter has reached 14 and becomes 0 by the input of thenext writing end signal, and the carry flag holder 203 is reset when theread block counter 202 counts 15, namely, when the count value of theread block counter has reached 14 and becomes 0 by the input of the nextcoding end signal. The carry flag holder 203 outputs a signal S253 tothe selector 204, which signal S253 is in the Hi state when the holder203 is in the set state and in the Lo state when the holder 203 is inthe reset state.

When the selector 204 is supplied with the value 0 (signal S254 a) andthe value 15 (signal S254 b), it selects one of these values accordingto the signal S253 supplied from the carry flag holder 203, and outputsthe selected value to the adder 205. The selector 204 selects 0 when thesignal S253 is in the Lo state while it selects 15 when the signal S253is in the Hi state.

The adder 205 adds the count value (signal S251) of the write blockcounter 201 and the value (signal S255) output from the selector 204,and outputs the result (signal S256) to the 202 from the sum (signalS256) output from the adder 205. The subtracter 206 outputs a signalS257 indicating the result obtained by the subtraction to the first andsecond comparators 206 and 207. Accordingly, the carry flag holder 203,the selector 204, and the adder 205 function as an addition controldevice which outputs an addition enabling signal when the count of thestorage information (writing end signal. S164) is carried out by apredetermined number of times, and outputs an addition disabling signalwhen the count of the process information (coding end signal S165) iscarried out by a predetermined number of times, and as a storageinformation count value change device which adds a predetermined value(signal S255) to the storage information count value (count value of thewrite block counter 201) according to the addition enabling signal orthe addition disabling signal to generate a storage information countvalue after processing (signal S256). Further, the subtracter 206functions as a codable unit number generating device which subtracts theprocess information count value (signal S252) from the storageinformation count value after processing (signal S256) to generate acodable unit number (signal S257).

The first and second comparators 207 and 208 receive a signal S258 aindicating 15 and a signal S258 b indicating 0, respectively. Thecomparator 207 compares the signal S258 a with the signal S257 while thecomparator 208 compares the signal S258 b with the signal S257 to decidewhether these signals match each other or not. According to the resultof the comparison, the comparator 207 generates a signal S259 indicatingwhether the signal S258 a matches the signal S257 or not, and outputs itto the error flag holder 209. According to the result of the comparison,the comparator 208 generates a signal S260 indicating whether the signalS258 b matches the signal S257 or not, and outputs it to the empty flagholder 210.

The error flag holder 209 is set when the signal S259 supplied from thecomparator 207 indicates “match”, namely, when the signal S257 is 15,and it is reset when an error reset signal SI 63b output from the imageinput controller 102 (FIG. 1) is input thereto. The error flag holder209 outputs an error flag S162 in the Hi state when it is in the setstate while it outputs an error flag S162 in the Lo state when it is inthe reset state, to the image input controller 102 (FIG. 1).

The empty flag holder 210 generates an empty flag S165 in the Hi statewhen the signal S260 supplied from the comparator 208 indicates “match”,that is, when the signal S257 is 0. The empty flag S165 is output to theencoder 104 as shown in FIG. 1.

Accordingly, the first comparator 207 and the error flag holder 209function as a first control information generating device which comparesthe codable unit number (signal S257) with a first prescribed value(signal S258 a), and generates the first control information (error flagS162 in the Hi state) when these signals match. Further, the secondcomparator 208 and the empty flag holder 210 function as a secondcontrol information generating device which compares the codable unitnumber (signal S257) with a second prescribed value (signal S258 b), andgenerates the second control information (empty flag S165 in the Histate) when these signals match. Further, the error flag S162 in the Histate is used as storage stop information indicating that storage of theinput image data should be stopped, and the empty flag S165 in the Histate is used as coding stop information indicating that coding shouldbe stopped.

FIG. 3 is a diagram showing an example of a format of digital image datain the image processing apparatus according to the first embodiment. Thedigital image data output from the A/D converter 101 possessed by theimage processing apparatus according to this first embodiment isdiscrete unit digital data, and it is an array of pixels having pixelvalues each showing a luminance signal or a color difference signal ofan image. As shown in FIG. 3(a), one frame comprises 352×240 pixels.FIG. 3(b) shows coded blocks, each coded block being a processing unitof coding by the encoder 104 and comprising 16×16 pixels. As shown inthe figure, one frame of digital image data comprises 22 coded blocks inthe horizontal direction and 15 coded blocks in the vertical direction.FIG. 3(c) shows slices, each slice being an input/output unit of digitalimage data according to this first embodiment. One slice is one array ofcoded blocks in the horizontal direction. As shown in the figure, oneslice comprises 22 coded blocks in the horizontal direction and 1 codedblock in the vertical direction, and one frame comprises 15 slices.

In this first embodiment, input/output of digital image data in/from theinput image memory 105 is managed in units of slices. Therefore, each ofthe unit storage amount and the unit processing amount is one slice.

Hereinafter, a description will be given of the operation of the imageprocessing apparatus according to the first embodiment constructed asshown in FIGS. 1 and 2. In the initial state, since system reset isperformed, the count values of the write block counter 201 (FIG. 2) andthe read block counter 202 (FIG. 2) possessed by the flag generator 107(FIG. 1) become 0, and the carry flag holder 203 (FIG. 2) and the errorflag holder 209 (FIG. 2) are in their reset states. Accordingly, theerror flag S162 output from the flag generator 107 shown in FIG. 1 is inthe ineffective state, namely, the Lo state.

In the initial state, the flag generator 107 shown in FIG. 2 operates asfollows. The signal S251 indicating 0 is output from the write blockcounter 201 to the adder 205. In this case, since the carry flag holder203 is in the reset state, the signal S253 is in the Lo state, 0 isselected in the selector 204, and the signal S255 indicating 0 is outputto the adder 205. In the adder 205, the signal S251 (0) and the signalS255 (0) are added, and the signal S256 indicating 0 which is the resultof the addition is output to the subtracter 206 on the other hand, fromthe read block counter, the signal S252 indicating the count value 0 isoutput to the subtracter 206. The subtracter 206 subtracts the signalS252 (0) from the signal S256 (0), and outputs the signal S257indicating 0 which is the result of the subtraction, to the comparators207 and 208.

The comparator 207 compares the signal S257 (0) with the signal S258 aindicating the constant 15. Since these signals do not match, thecomparator 207 does not perform the setting operation for the error flagholder 209. Therefore, the error flag holder 209 remains in the resetstate, and the output error flag S162 remains in the Lo state.

On the other hand, in the comparator 208, the signal S257 (0) iscompared with the signal S258 b indicating the constant 0. Since thesesignals match, the comparator 208 outputs the signal S260 indicating“match” to the empty flag holder 210. Thereby, the empty flag holder 210outputs the empty flag S165 in the Hi state.

The empty flag S165 in the Hi state means that digital image data to becoded is not stored in the input image memory 105. The empty flag S165is input to the encoder 104 as shown in FIG. 1, and the encoder 104 doesnot perform coding when the empty flag S165 is in the Hi state.Accordingly, the encoder 104 is in the stand-by state until a prescribedamount of data is stored in the input image memory 105.

As shown in FIG. 1, when the analog video signal S151 is input to theimage processing apparatus, the analog video signal S151 is input to theA/D converter 101 and subjected to analog/digital conversion. The A/Dconverter 101 outputs the digital image data S152 so generated to theimage input controller 102. The image input controller 102 reads theerror flag S162 supplied from the flag generator 107. As describedabove, since the error flag S162 is in the ineffective state (Lo state),the image input controller 102 generates an image input enabling signalS161 corresponding to the input digital image data S152 as a signalindicating “effective” (Hi state), and outputs the digital image dataS153 and the image input enabling signal S161 to the memory controller103.

Since the image input enabling signal S161 indicates “effective”, thememory controller 103 stores the corresponding digital image data S152in the input image memory 105. As already described with respect to FIG.3, input/output of the digital image data in/from the input image memoryis carried out in slice units (FIG. 3(c)). So, when the memorycontroller 103 has stored one slice of digital image data in the inputimage memory, it generates a writing end signal S164 to be output to theflag controller 107.

In the flag generator 107, the writing end signal S164 is input to thewrite block counter 201 as shown in FIG. 2, and the write block counterperforms the count-up operation to increase its count value by 1. In thefigure, since the count value of the write block counter 201 changesfrom 0 to 1, the signal S251 indicating 1 is output from the write blockcounter 201 to the adder 205. Since the carry flag holder 203 remains inthe reset state, 0 is selected in the selector 204 according to thesignal S253 indicating the reset state, and the signal S255 indicating 0is output to the adder 205. In the adder 205, the signal S251 (1) andthe signal S255 (0) are added, and the signal S256 indicating 1, whichis the result of the addition, is output to the subtracter 206. On theother hand, the count value of the read block counter is 0, and so thesignal S252 indicating 0 is output to the subtracter 206. The subtracter206 subtracts the signal S252 (0) from the signal S256 (1), and outputsthe signal S257 indicating 1, which is the result of the subtraction, tothe comparators 207 and 208.

The comparator 207 compares the signal S257 (1) with the signal S258 aindicating the constant 15. Since these signals do not match, thecomparator 207 does not perform the setting operation for the error flagholder 209. Accordingly, the error flag holder 209 remains in the resetstate, and the output error flag S162 remains in the Lo state.

On the other hand, the comparator 208 compares the signal S257 (1) withthe signal S258 b indicating the constant 0. Since these signals do notmatch, the comparator 208 outputs the signal S260 indicating “mismatch”to the empty flag holder 210. Thereby, the empty flag holder 210 outputsthe empty flag S165 in the Lo state.

Turning to FIG. 1, the empty flag S165 in the Lo state is input to theencoder 104. Since the empty flag S165 in the Lo state indicates thatdigital image data to be subjected to coding is stored in the inputimage memory 105, the encoder 104 executes coding when detecting thisflag. The digital image data stored in the input image memory 105 isread by the encoder 104 through the memory controller 103. The encoder104 codes the input digital image data S155 to generate coded data S156,and outputs the data to the rate buffer 106. From the rate buffer 106,the coded data S157 is output at a constant rate to the outside of theimage processing apparatus.

On the other hand, when coding of the one slice of digital image datahas been completed, the encoder 104 generates a coding end signal S166indicating the completion, and outputs this signal to the flag generator107. In the flag generator 107, the coding end signal S166 is input tothe read block counter 202 as shown in FIG. 2, and the read blockcounter 202 performs the count-up operation to increase its count valueby 1.

Thereafter, the image input controller 102 checks the state of the errorflag S162, and the digital image data is continuously stored in theinput image memory 105 as long as the error flag is in the Lo state. Onthe other hand, the encoder 104 checks the state of the empty flag S165every time one slice of digital image data is coded. When the empty flagis in the Lo state, the encoder 104 reads the digital image data storedin the in put image memory 105 and codes the data.

In the flag generator 107, the write block counter 201 shown in FIG. 2performs the count-up operation every time the writing end signal S164output from the memory controller 103 (FIG. 1) is input thereto. Whenthe count value has reached 14 and a further writing end signal S164 hasbeen input, the write block counter 201 instructs the carry flag holder203 to be in the set state, and sets its own count value to 0. In otherwords, the carry flag holder 203 goes into the set state when the countvalue of the write block counter 201 becomes 15 which is equal to thenumber of slices constituting one frame (FIG. 3(c)).

The read block counter 202 shown in FIG. 2 performs the count-upoperation every time the coding end signal S166 output from the encoder104 (FIG. 1) is input thereto. When the count value has reached 14 and afurther coding end signal S166 has been input, the read block counter202 instructs the carry flag holder 203 to be in the reset state, andsets its own count value to 0. In other words, the carry flag holder 203goes into the reset state when the count value of the read block counter202 becomes 15 which is equal to the number of slices constituting oneframe (FIG. 3(c)).

When the carry flag holder 203 is in the set state, as the signal S253is in the Hi state, the selector 204 selects the signal S254 bindicating 15 and outputs the signal S255 indicating 15 to the adder205. In this case, in the adder 205, 15 is added to the count value ofthe write block counter 201, and the result of the addition S256 isoutput to the subtracter 206.

The result obtained in the subtracter 206 is a difference between “thenumber of slices stored in the input image memory 105” (S251=S256) and“the number of slices coded by the encoder 104” (S252) when the carryflag holder 203 is in the reset state. On the other hand, when the carryflag holder 203 is in the set state, the result is a difference between“the number of slices stored in the input image memory 105+15”(S251+15=S256) and “the number of slices coded by the encoder 104”(S252). When this difference is 0, the empty flag S165 is in the Histate, and the coding by the encoder 104 is stopped. When the differenceis 15, the error flag S162 is in the Hi state, and the image inputcontroller 102 generates an image input enabling signal S161 indicating“ineffective”, and therefore storage of digital image data in the inputimage memory is not carried out.

FIGS. 4 and 5 are timing charts showing examples of processing states ofthe image processing apparatus according to the first embodiment. InFIGS. 4 and 5, “image input enabling signal S161” is a signal generatedby the image input controller 102 to be output to the memory controller103 in FIG. 1, and its Hi state indicates “effective” and instructsstorage of digital image data in the input image memory while its Lostate indicates “ineffective” and does not instruct storage of digitalimage data in the input image memory 105. “Digital image data S153”indicates digital image data in slice units to be output to the memorycontroller 103 together with the image input enabling signal S161.

In FIGS. 4 and 5, “write block counter 201” indicates the count valuepossessed by the write block counter 201 in FIG. 2. The write blockcounter 201 counts the writing end signal S164 which is output from thememory controller 103 shown in FIG. 1 and indicates that storage ofdigital image data for each slice has been performed, and the countvalue corresponds to the number of slices of digital image data storedin the input image memory 105.

In FIGS. 4 and 5, “carry flag (S253)” indicates the state of the signalS253 indicating whether the carry flag holder 203 is in the set state orin the reset state, in FIG. 2. As described above, the signal S253 is inthe Hi state when the holder 203 is in the set state while it is in theLo state when the holder 203 is in the reset state, and this signalcontrols the selection of the selector 204.

In FIGS. 4 and 5, “empty flag S165” indicates the state of a signalwhich is generated by the flag generator 107 and output to the encoder104 in FIG. 1, and its Hi state indicates that no digital image data tobe coded is stored in the input image memory 105, and instructs theencoder 104 to stop coding. Its Lo state indicates that digital imagedata to be coded is stored in the input image memory 105, and instructsthe encoder 104 to execute coding.

In FIGS. 4 and 5, “error flag S162” indicates the state of a signalwhich is generated by the flag generator 107 and output to the imageinput controller 102 in FIG. 1, and its Hi state indicates overflow inthe input image memory 105, and instructs the image input controller 102to generate an image input enabling signal indicating “ineffective” (tostop storage of data in the input image memory 105). Its Lo stateindicates that storage of data in the input image memory 105 ispossible, and instructs the image input controller 102 to generate animage input enabling signal indicating “effective” (to execute storageof data in the input image memory 105).

In FIGS. 4 and 5, “read block counter 202” indicates the count valueheld by the read block counter 202, in FIG. 2. The read block counter202 counts the coding end signal S166 which is output from the encoder104 shown in FIG. 1 and indicates that coding for each slice has beenperformed, and the count value corresponds to the number of slices ofdigital image data which have been coded.

In FIGS. 4 and 5, “coding process (104)” indicates the coding process inslice units performed by the encoder 104. The time required for codingof digital image data significantly varies according to thecharacteristics of the image and, therefore, there are both cases wherethe time required for processing one slice is long and where it isshort, as shown in FIGS. 4 and 5.

Hereinafter, the image processing by the image processing apparatusaccording to the first embodiment will be described along the timingchart of FIG. 4.

Since no effective region of the image is input until timing t40 shownin FIG. 4, the image input controller 102 outputs the image inputenabling signal S161 in the Lo state, and storage of digital image datais not carried out. From timing t40, the first frame of digital imagedata S153 is input to be processed. Since the error flag S162 is in theLo state in the initial state, the image input controller 102 generatesan image input enabling signal S161 in the Hi state indicating“effective”, so that the digital image data S153 is stored in the inputimage memory 105.

Every time one slice of data is stored, the memory controller 103outputs a writing end signal S164 to the flag generator 107, and thewrite block counter 201 possessed by the flag generator 107 performs thecount-up operation corresponding to the signal S164. Here, every timethe slices constituting the digital image data of the first frame (15slices from 0 to 14) are input, the count value increases to 14.

At timing t41 when one slice of the digital image data S153 has beenstored, the count value of the write block counter 201 changes from 0 to1 as described above, whereby the empty flag changes from the Hi stateto the Lo state. Accordingly, the encoder 104, detecting that the emptyflag is in the Lo state, reads the digital image data stored in theinput image memory 105 to code the data. Every time coding of one slicehas ended, a coding end signal S166 is output, and the read blockcounter 202 possessed by the flag generator 107 performs the count-upoperation corresponding to the signal S166.

Between timing t41 and timing t42, coding is carried out speedily and,immediately after t42, the input image memory 105 enters in the statewhere the digital image data to be subjected to coding has not yet beencompletely stored therein. In this case, since the value of the signalS257 output from the subtracter 206 shown in FIG. 2 becomes 0, the emptyflag in the Hi state is output according to the result of the comparisonin the comparator 208. Therefore, as shown in FIG. 4, the encoder 104stops coding. Here, when the next slice is stored in the input imagememory 105, the empty flag S165 returns to the Lo state, and coding isresumed.

Until timing t43, the first frame of digital image data S153 has beenstored in the input image memory 105. At this time, since the writeblock counter 201 receives the writing end signal S164 while it holdsthe count value 14, the counter 201 instructs the carry flag holder 203shown in FIG. 2 to be in the set state and sets its own count value to0. Thereby, the signal S253 output from the carry flag holder 203 goesinto the Hi state, and in the adder 205, 15 is added to the count valueof the write block counter 201.

At timing t44, the second frame of digital image data S153 is input.Since the error flag S162 remains in the Lo state, the image inputcontroller 102 outputs the image input enabling signal S161 indicating“effective”, whereby the first slice of the input digital image data isstored so that it overwrites the already coded slice of digital imagedata in the first frame, under control of the memory controller 103. Thesubsequent slices of the digital image data S153 are also stored in theinput image memory 105 so that these slices overwrite the already codedslices. Thereafter, at timing t45, the encoder 104 completes coding ofthe digital image data in the first frame. The read block counter 202(count value 14) receiving the coding end signal S166 at this timeresets the carry flag holder 203 shown in FIG. 2 and sets its own countvalue to 0. Therefore, the signal S253 shown in FIG. 4 goes into the Lostate, and in the adder 205 the value to be added to the write blockcounter 201 is changed from 15 to 0.

As described above, in the image processing apparatus of the firstembodiment, even when the input image memory 105 having a capacity forone frame comes into the state where one frame of data has already beenstored, the subsequent one frame of data is processed so that itoverwrites in slice units, in contrast with the prior art imageprocessing apparatus in which one frame of data is immediatelydiscarded. To be specific, in the prior art image processing apparatus,the second frame of digital image data shown in FIG. 4 is discardedwithout being coded. However, in the image processing apparatusaccording to the first embodiment, the second frame of data is notdiscarded but coded according to the above-mentioned processing.

However, also in the image processing apparatus of this firstembodiment, there is a case where digital image data is discardedaccording to control using an error flag. FIG. 5 is a diagram forexplaining processing in this case.

In FIG. 5, from timing t50, the i-th frame of digital image data S153 isstored in the input image memory 105 and, thereafter, the encoder 104starts coding. At timing t51, storage of the i-th frame of digital imagedata S153 is completed. As in the case shown in FIG. 4, the signal S253output from the carry flag holder 203 goes into the Hi state and, fromtiming t52, the (i+1)th frame of digital image data is stored so that itoverwrites the already coded data. At timing t53, the 11th slice of datain the (i+1)th frame is to be stored, but coding of the 11th slice ofdata in the i-th frame has not yet been completed at this point of time.

In such case, in FIG. 2, the count value 11 of the write block counterand the value 15 output from the selector 204 are added by the adder205, and the value 26 (signal S256) is output to the subtracter 206. Onthe other hand, the count value of the read block counter 202 becomes11, and the signal S252 indicating 11 is output to the subtracter 206.The result obtained by the subtracter 206 becomes 26−11=15, and thesignal S257 having the value 15 is output to the comparator 207, wherebythe error flag S162 goes into the Hi state. Since the error flag S162 isHi as shown in FIG. 5, the image input controller 102 sets the imageinput enabling signal S161 in the Lo state indicating “ineffective”. So,the digital image data is discarded without being stored in the inputimage memory 105. Accordingly, the 11th and subsequent slices of digitalimage data in the i-th frame, for which coding has not completed yet,are stored without being overwritten.

At timing t54, the image input controller 102 outputs the counter resetsignal S163 to the flag generator 107. The write block counter 201 shownin FIG. 2 sets the count value to 0 in response to the signal S163 a.The number of slices of digital image data stored in the input imagememory 105 indicates the number of remaining slices which have not yetbeen coded, amongst the slices constituting the i-th frame of digitalimage data.

Timing t55 is the timing at which storage of the (i+1)th frame ofdigital image data ought to be completed if the processing has beencarried out normally. At this point of time, the image input controller102 shown in FIG. 1 outputs the error reset signal S163 to the flaggenerator 107. As shown in FIG. 2, the error reset signal S163 b isinput to the error flag holder 209, whereby the state of the error flagholder 109 is changed from the set state to the reset state.Accordingly, the error flag output from the flag generator 107 changesfrom the Hi state to the Lo state.

Further, at timing t56, the read block counter 202 holding the countvalue 14 receives the coding end signal S166, and it changes the stateof the carry flag holder 203 to the reset state and sets its own countvalue to 0. Accordingly, the signal S253 output from the carry flagholder 203 changes from the Hi state to the Lo state, and 0 is added inthe adder 205 shown in FIG. 2. Accordingly, both of the signal S256 andthe signal S252 become 0 and the signal S257 becomes 0, whereby theempty flag S165 in the Hi state is output.

In response to this, the encoder 104 stops coding and, as shown in FIG.5, the coding stop period continues until the subsequent data is stored.

At timing t57, the (i+2)th frame of digital image data S153 is stored inthe input image memory 105. Thereby, in FIG. 2, the count value of thewrite block counter 201 changes from 0 to 1, and the value of the signalS257 changes from 0 to 1, whereby the empty flag S165 in the Lo state isoutput. Accordingly, as shown in FIG. 5, on and after timing t57 whenthe empty flag S165 goes in the Lo state, coding by the encoder 104 isresumed to process the (i+2)th frame of data.

In the image processing apparatus according to the first embodiment,since the overwrite storage in slice units is carried out as shown inFIG. 4, the second frame of digital image data is not discarded evenwhen coding is delayed. However, as shown in FIG. 5, when the delayincreases and the overwrite storage in slice units adversely affects theunprocessed data in the i-th frame, the (i+1)th frame of data is notsubjected to coding in the above-described processing to protect thei-th frame of data, and subsequently the (i+2)th frame of data issubjected to coding.

As described above, since the image processing apparatus according tothe first embodiment is provided with the flag generator 107 which holdsa carry flag in it and generates an error flag and an empty flag, theencoder 104 starts coding in accordance with the state of the emptyflag. Therefore, the coding can be started when one slice of digitalimage data has been stored in the input image memory 105, whereby adelay until starting the coding can be reduced as compared with theprior art image processing apparatus which requires storage of data inone frame (in the image format shown in FIG. 3, 15 slices), resulting inan image processing apparatus suitable for the real-time use.

A description is now given of comparison of delays between the imageprocessing apparatus according to the first embodiment and the imageprocessing apparatus according to the prior art. According to generalconditions, it is assumed that the target to be processed is accordingto the NTSC (1 line=about 63.5 us) system, the image size to be storedin the input image memory is 352 pixels×240 pixels (352 pixels×240lines) for one frame, and the slice size (the processing unit of thefirst embodiment) is 352 pixels×16 pixels (352 pixels×16 lines) for oneslice. In this case, in the prior art image processing apparatus, thetime required for storing one frame of image data in the input imagememory is 240 lines×63.5 us, that is, about 15 ms. Since coding is notstarted until one frame of data has been stored as described above, thedelay time from which image capture is started to when coding is startedis about 15 ms. On the other hand, in the image processing apparatusaccording to the first embodiment, the time required for storing oneslice of image data in the input image memory is 16 lines×63.5us, thatis, about 1 ms. This “about 1 ms” is the delay time until when coding isstarted and, therefore, the delay is significantly reduced as comparedwith the prior art.

Further, since the input image memory 105 is managed in slice units, amemory capacity enough to store one frame suffices. Since this capacityis smaller than that of the prior art image processing apparatus whichrequires a capacity enough to store at least two frames, the device costcan be reduced.

Furthermore, since the flag generator 107 holds a carry flag, overwritein slice units can be performed on the input image memory 105. So, evenwhen coding is delayed, the possibility of frame discard is reduced,resulting in improved image quality.

Embodiment 2

An image processing apparatus according to a second embodiment of theinvention controls image processing by using control flags as in thefirst embodiment, but this second embodiment employs the number ofremaining block units in place of the empty flag employed in the firstembodiment.

FIG. 6 is a block diagram illustrating the structure of an imageprocessing apparatus according to the second embodiment. As shown in thefigure, the image processing apparatus according to the secondembodiment comprises an A/D converter 601, an image input controller602, a memory controller 603, an encoder 604, an input image memory 605,a rate buffer 606, and a flag generator 607. This apparatus receives ananalog video signal S651 and outputs coded data S657. The encoder 604 ofthe image processing apparatus according to this second embodimentincludes a loop setting unit 6041 and an interrupt processing unit 6042.As in FIG. 1 of the first embodiment, signals shown by solid lines aredata to be processed, and signals shown by broken lines are signals forcontrol.

The image input controller 602 generates an image input enabling signalindicating whether the input digital image data is effective orineffective. The image input controller 602 of this second embodimentgenerates an image input enabling signal according to the distinctionbetween the effective region and the ineffective region of the digitalimage data as in the case of the prior art image processing apparatus.Further, it refers to an error flag supplied from the flag generator 607described later, like the input image controller 102 of the firstembodiment. Also in this second embodiment, as in the first embodiment,the image input controller 602 generates an image input enabling signalindicating “effective” when the error flag is ineffective (Lo state),and generates an image input enabling signal indicating “ineffective”when the error flag is effective (Hi state).

The encoder 604 subjects the digital image data to a predeterminedcompressive coding process to generate coded data. The loop setting unit6041 included in the encoder 604 sets the loop number indicating thenumber of coding processes to be executed continuously, according to theremaining block number S665 supplied from the flag generator 607described later. The interrupt processing unit 6042 included in theencoder 604 resets the loop number possessed by the loop setting unit6041, according to the error flag supplied from the flag generator 607.The encoder 604 of this second embodiment does not perform coding whenthe value of the remaining block number S665 is 0. When it is not 0, theencoder 604 successively codes the digital image data in the slicenumber equivalent to the loop number of the loop setting unit 6041. Likethe encoder 104 according to the first embodiment, the encoder 604outputs a coding end signal S666 to the flag generator 607 every timecoding of one slice is completed.

The flag generator 607 counts the writing end signal for each slicesupplied from the memory controller 603 and the coding end signal foreach slice supplied from the encoder 604 and, according to the result ofthe counting, it generates flags (remaining block number and error flag)used for controlling data input/output in/from the memory. The flaggenerator 607 according to this second embodiment generates continuousprocess information (remaining block number) indicating how many timesthe coding of the unit processing amount (one slice) can be continuouslyexecuted by the coding device (the encoder 604).

The A/D converter 601, the memory controller 603, the input image memory605, and the rate buffer 606 are identical to 101, 103, 105, and 106according to the first embodiment, respectively.

FIG. 7 is a block diagram illustrating the internal structure of theflag generator 607 (FIG. 6). As shown in the figure, the flag generator607 comprises a write block counter 701, a read block counter 702, acarry flag holder 703, a selector 704, an adder 705, a subtracter 706, afirst comparator 707, an error flag holder 709, and a remaining blocknumber holder 710. The remaining block number holder 710 holds theresult output from the subtracter 706 as a remaining block number (m)which indicates, in slice units, the amount of digital image data to besubjected to coding.

The write block counter 701, the read block counter 702, the carry flagholder 703, the selector 704, the adder 705, the subtracter 706, thefirst comparator 707, and the error flag holder 709 are identical tothose (201-207, and 209) shown in FIG. 2 according to the firstembodiment.

Hereinafter, a description will be given of the operation of the imageprocessing apparatus of the second embodiment so constructed. Also inthis second embodiment, as in the first embodiment, the image data shownin FIG. 3 is used as a target to be processed.

In the initial state, system reset is performed as in the firstembodiment, whereby the count values of the write block counter 701(FIG. 7) and the read block counter 702 (FIG. 7) possessed by the flaggenerator 607 (FIG. 6) become 0, and the carry flag holder 703 (FIG. 7)and the error flag holder 709 (FIG. 7) are in the reset state.Accordingly, the error flag S662 in the ineffective state, i.e., the Lostate, is output. Further, since the count value of the write blockcounter 701 is 0, the values of the signals S751, S756, and 5757 are 0.Accordingly, the remaining block number m possessed by the remainingblock number holder is 0, and a signal S665 indicating 0 is output tothe encoder 604. The encoder 604 receiving the remaining block numberS665 does not perform coding because the value of this signal is 0.

As shown in FIG. 6, when the analog video signal S651 is input to theimage processing apparatus, this analog video signal S651 is input tothe A/D converter 601, wherein it is subjected to analog/digitalconversion. The A/D converter 601 generates digital image data S652 andoutputs this data to the image input controller 602. Since the errorflag S662 is in the ineffective state (Lo state), the image inputcontroller 602 generates an image input enabling signal S661corresponding to the input digital image data S652 as a signalindicating “effective” (Hi state), and outputs both of the digital imagedata S653 and the image input enabling signal S661 to the memorycontroller 603. Since the image input enabling signal S661 indicates“effective”, the memory controller 603 stores the corresponding digitalimage data S652 in the input image memory 605. When one slice of datahas been stored, the memory controller 603 outputs the writing endsignal S664 to the flag generator 607.

In the flag generator 607 shown in FIG. 7, since the count value of thewrite block counter 701 changes from 0 to 1, the values of the signalsS751, S756, and S757 change from 0 to 1, and the remaining block numberm changes from 0 to 1. The signal S665 indicating 1 is output to theencoder 604. Therefore, when the encoder 604 has ended coding for oneslice, it outputs the coding end signal S666 to the flag generator 607.

When the encoder 604 receives the signal S665 indicating the remainingblock number (m) is other than 0, it sets the value m as the loop numberto the loop setting unit 6041 included in the encoder 604. When codingfor one slice of digital image data has ended, the encoder 604 decreasesthe loop number by 1, and continuously performs coding on the next oneslice of digital image data, without detecting the signal S665indicating the remaining block number, until the loop number reaches 0.When the loop number becomes 0, the encoder 604 detects the signal S665to obtain the remaining block number m, and sets the loop number.

Although the encoder 104 according to the first embodiment must detectthe state of the empty flag each time one slice of digital image data iscoded, the encoder 604 according to this second embodiment detects thesignal S665 indicating the remaining block number only when the loopnumber has become 0 and, therefore, the frequency of detection isreduced, resulting in highly efficient processing.

Thereafter, the image input controller 602 checks the state of the errorflag S662. While the error flag is in the Lo state, the digital imagedata is continuously stored in the input image memory 605. On the otherhand, the encoder 604 executes coding as described above.

In response to the storage and coding of the digital image data, thecount values of the write block counter 701 and the read block counter702 of the flag generator 607 are updated, and the value of the signalS757 indicating a difference between them is regarded as the remainingblock number m. Further, set and reset of the carry flag holder 703 areperformed in like manner as described for the first embodiment. In theset state, in the adder 705, 15 is added to the count value of the writeblock counter 701. When the value of the signal S757 has become 15, theerror flag S662 goes into the Hi state, and the input controller 602generates an image input enabling signal indicating “ineffective” sothat the digital image data is not stored in the input image memory.

FIGS. 8 and 9 are timing charts showing examples of processing states ofthe image processing apparatus according to the second embodiment. InFIGS. 8 and 9, “remaining block number m” indicates the value of thesignal S665 which is held by the remaining block number holder 710 shownin FIG. 7 and is output from the flag generator 607 to the encoder 604in FIG. 6. In FIGS. 8 and 9, “image input enabling signal S661”,“digital image data S653”, “write block counter 701”, “carry flag(S753)”, “error flag S662”, “read block counter 702”, and “codingprocess (604)” are identical to those shown in FIGS. 4 and 5 accordingto the first embodiment.

Hereinafter, the image processing of the image processing apparatusaccording to the second embodiment will be described with reference tothe timing chart of FIG. 8.

Since the effective region of the image has not been input until timingt80 shown in the figure, the image input controller 602 outputs theimage input enabling signal S661 in the Lo state, and so storage ofdigital image data is not carried out. From timing t80, the first frameof digital image data S653 is input to be processed. In the initialstate, since the error flag S662 is in the Lo state, the image inputcontroller 602 generates an image input enabling signal S661 in the Histate indicating “effective”, whereby the digital image data S653 isstored in the input image memory 605. Each time one slice of data isstored, the writing end signal S664 is output from the memory controller603 to the flag generator 607, and the write block counter 701 possessedby the flag generator 607 performs the count-up operation in response tothe signal S664. To be specific, each time the slices constituting thefirst frame of digital image data (15 slices from 0 to 14) are input,the count value increases to 14.

At timing t81, the remaining block number m changes from 0 to 1. Theencoder 604 receiving the signal S665 sets the loop number of 1 in theloop setting unit 6041, and performs coding on the one slice of digitalimage data. Then, the loop number is decreased by 1, and so the loopnumber is changed from 1 to 0. Since the loop number has become 0, theencoder 604 detects the signal S665 at timing t82 to obtain theremaining block number m.

Thereafter, coding is carried out speedily and, at timing t83, theremaining block number m becomes 0. The encoder 604, which has detectedthe signal S665 to obtain the remaining block number m, stops codingbecause m is 0. When the remaining block number m changes from 0 to 1,the encoder 604 detects the signal S665 indicating this change and thenresumes the coding.

At timing t84, the encoder 604 obtains the remaining block number m=3.At this time, the loop number of 3 is set in the loop setting unit 6041.Then, the encoder 604 codes one slice of digital image data S163 storedin the input image memory 105 (the seventh slice in the first frame),and sets the loop number to 2 by decreasing it by 1. The encoder 604codes the next one slice (the eighth slice) without detecting the signalS665, and sets the loop number to 1. Since the loop number is not 0, theencoder 604 codes the next one slice (the ninth slice) without detectingthe signal S665, and sets the loop number to 0. Since the loop numberhas become 0, the encoder 604 detects the signal S665 to obtain 6 as theremaining block number m. Then, the loop number is set to 6, and thesame processing as described above is repeated.

At timing t85, since the writing end signal S663 is input when the countvalue of the write block counter 701 is 14, the carry flag holder 703goes into the set state, and the signal S753 becomes Hi. Thereby, in theflag generator 607, 15 is added to the count value of the write blockcounter 701, as described for the first embodiment.

Accordingly, as in the first embodiment, even when the second frame ofdigital image data is input though coding of the first frame of digitalimage data has not yet ended, the second frame of data is stored so thatit overwrites the first frame of data in slice units, in contrast withthe prior art image processing apparatus in which the second frame ofdata is discarded.

Thereafter, at timing t86, since the coding end signal S666 is inputwhen the count value of the read block counter 702 is 14, the carry flagholder 703 goes into the reset state, whereby the signal S753 goes intothe Lo state.

Also in the image processing apparatus of this second embodiment, as inthe first embodiment, there is a case where the digital image data isdiscarded according to the control using an error flag, and FIG. 9 is adiagram for explaining the processing in this case.

In FIG. 9, from timing t90, the i-th frame of digital image data S653 isstored in the input image memory 605 and, thereafter, the encoder 604starts coding. At timing t91, storage of the digital image data S653 inthe i-th frame is completed. As in the case of FIG. 8, the signal S753output from the carry flag holder 703 goes into the Hi state and, fromtiming t92, the (i+1)th frame of digital image data is stored so that itoverwrite the already coded data, as in the case of FIG. 8. At timingt93, although the 11th slice of data in the (i+1)th frame ought to bestored, coding of the 11th slice of data in the i-th frame has not yetended at this point of time.

In this case, as in the first embodiment described using FIG. 5, theerror flag S662 goes in the Hi state, and the image input controller 602sets the image input enabling signal S661 in the Lo state indicating“ineffective”, and therefore the digital image data S653 is not storedin the input image memory 605. Accordingly, the 11th and subsequentslices of digital image data in the i-th frame, for which coding has notended yet, are stored without being overwritten.

Further, as in the first embodiment, since the counter reset signal S663a is output, the count value of the write block counter 701 becomes 0.Further, in FIG. 7, the signal S751 becomes 0 in FIG. 7, and the signalS756 obtained by adding 15 in the adder 705 becomes 15. Since the countvalue 11 of the read block counter 702 is input to the subtracter 706,the value of the signal S757 becomes 4 which is the result of thesubtraction, and the remaining block number m becomes 4 as well.

Since the error flag S662 in the Hi state is output to the interruptprocessing unit 6042 included in the encoder 604 as shown in FIG. 6, theinterrupt processing unit 6042 receives the signal S665 indicating theremaining block number m to obtain the remaining block number m. Insidethe encoder 604, resetting of the loop number possessed by the loopsetting unit 6041 is carried out by using the remaining block number m.The remaining block number m is stored in the input image memory 605,and indicates the number of slices in the i-th frame which has not beencoded yet. So, the encoder 604 performs coding continuously for thenumber of the slices and, at timing t95, the coding of the data in thei-th frame is completed.

On the other hand, at timing t94, as in the first embodiment, the errorflag holder 709 goes into the reset state by the error reset signal S663b (FIG. 7), and the error flag S662 (FIG. 9) goes into the Lo state.

Since the remaining block number m at timing t95, which is detected fromthe signal S665 by the encoder 604 after the continuous coding, is 0,the encoder 604 stops coding. Thereafter, at timing t96 when one sliceof digital image data S653 in the (i+2)th frame is stored, coding isresumed because the remaining block number m becomes 1.

As described above, according to the image processing apparatus of thesecond embodiment, the encoder 604 includes the loop setting unit 6041and the interrupt processing unit 6042, and the flag generator 607generates and outputs an error flag and a remaining block number, andthe encoder 604 starts coding according to the value of the remainingblock number m. Therefore, coding can be started after one slice ofdigital image data has been stored in the input image memory 605,whereby the delay until the start of coding can be reduced as comparedwith the prior art image processing apparatus which requires storage ofdata in one frame (15 slices in the image format shown in FIG. 3),resulting in an image processing apparatus suitable for the real-timeuse.

Further, since the input image memory 605 is managed in slice units, amemory capacity for storing one frame of data suffices. This capacity issmaller than that of the prior art image processing apparatus whichrequires a capacity for storing at least two frames of data and,therefore, the cost of the apparatus can be reduced.

Further, since the flag generator 607 holds the carry flag, overwritingin slice units can be performed in the input image memory 605.Therefore, even when coding is delayed, the possibility of discardingthe frame is reduced, resulting in improved image quality.

Further, in this second embodiment, since the encoder 604 performscoding continuously for the loop number possessed by the loop settingunit 6041 without detecting the signal S665, the processing efficiencyis improved as compared with the first embodiment in which the emptyflag is detected each time coding for one slice is completed.

Although both of the first and second embodiments employ the image datahaving the format shown in FIG. 3, the present invention is notrestricted thereto. For example, digital image data having any of thefollowing structures may be used as a target to be processed: horizontal352 pixels×vertical 288 pixels; horizontal 176 pixels×vertical 144pixels; horizontal 704 pixels×vertical 240 pixels; horizontal 704pixels×vertical 480 pixels; and horizontal 1020 pixels×vertical 1152pixels. Further, as a block to be coded, a block of 8 pixels×8 pixelsmay be used as a unit of coding. In these cases, the signal valueindicating the constant to be input to the selector 204 or 704 and thereference value to be input to the comparator 207 or 707 should beadaptively changed from those shown in the first and second embodiments,whereby the same effects as described above are obtained.

Furthermore, as image data to be a target to be processed, luminancedata, color difference data, RGB data or the like may be processed withthe same effects as described above.

Applicability in Industry

As described above, according to the present invention, in an imageprocessing apparatus or an image processing method for coding imagedata, since the delay time until start of coding is reduced, preferabledisplay is realized even when it is applied to the use requiring “realtime”, such as a visual telephone, a camera-display monitor or the like.

Furthermore, according to the present invention, a memory unit having arelatively small capacity can be used as a memory unit for temporarilystoring image data when the image data is subjected to coding, whereby alow-cost image processing apparatus is realized.

Moreover, according to the present invention, the possibility ofdiscarding image data to deal with the delay in coding is reduced, andthis reduction results in an image processing apparatus of improvedimage quality.

What is claimed is:
 1. An image processing apparatus for storing inputimage data and subjecting the stored image data to a coding process,said image processing apparatus comprising: a temporary storage meansfor storing the input image data; an image input control means forcontrolling storage of the input image data in said temporary storagemeans; a storage control means for executing storage of the image datain said temporary storage means under control of said image inputcontrol means and, when a predetermined unit storage amount of data hasbeen stored, generating storage information indicating this; a codingmeans for reading the image data stored in said temporary storage meansto subject the image data to a predetermined coding process and, when apredetermined unit processing amount of data has been subjected to thecoding process, generating process information indicating this; and acontrol information generating means for generating first controlinformation used by said image input control means to control thestorage, and generating second control information used by said codingmeans to control the coding process, in accordance with the storageinformation generated by said storage control means and the processinformation generated by said coding means.
 2. An image processingapparatus as defined in claim 1, wherein said control informationgenerating means generates, as the first control information, storagestop information indicating that the storage of the input image datashould be stopped, and generates, as the second control information,coding stop information indicating that the coding process should bestopped.
 3. An image processing apparatus as defined in claim 1, whereinsaid control information generating means generates, as the firstcontrol information, storage stop information indicating that thestorage of the input image data should be stopped, and generates, as thesecond control information, continuous process information indicatinghow many times said coding means can continuously perform the codingprocess on the unit processing amount of image data.
 4. An imageprocessing apparatus as defined in claim 1, wherein said controlinformation generating means comprises: a storage information countingmeans for counting the storage information and holding the result as astorage information count value; a process information counting meansfor counting the process information and holding the result of the countas a process information count value; an addition control means foroutputting an addition enabling signal when the count of the storageinformation is performed a predetermined number of times, and outputtingan addition disabling signal when the count of the process informationis performed a predetermined number of times; a storage informationcount value change means for adding a predetermined value to the storageinformation count value according to the addition enabling signal or theaddition disabling signal, thereby generating a storage informationcount value after processing; a codable unit number generating means forsubtracting the process information count value from the storageinformation count value after processing, thereby generating a codableunit number; a first control information generating means for comparingthe codable unit number with a first predetermined value and, when thesevalues match, generating the first control information; and a secondcontrol information generating means for comparing the codable unitnumber with a second predetermined value and, when these values match,generating the second control information.
 5. An image processingapparatus as defined in claim 1, wherein said control informationgenerating means comprises: a storage information counting means forcounting the storage information and holding the result as a storageinformation count value; a process information counting means forcounting the process information and holding the result as a processinformation count value; an addition control means for outputting anaddition enabling signal when the count of the storage information hasbeen performed a predetermined number of times, and outputting anaddition disabling signal when the count of the process information hasbeen performed a predetermined number of times; a storage informationcount value change means for adding a predetermined value to the storageinformation count value according to the addition enabling signal or theaddition disabling signal, thereby generating a storage informationcount value after processing; a codable unit number generating means forsubtracting the process information count value from the storageinformation count value after processing, thereby generating a codableunit number; and a first control information generating means forcomparing the codable unit number with a first predetermined value and,when these values match, generating the first control information;wherein the codable unit number is used as the second controlinformation.
 6. An image processing method for storing input image datain a temporary storage means, and subjecting the stored image data to acoding process, said image processing method comprising: an image inputcontrol step of controlling storage of the input image data in thetemporary storage means; a storage control step of executing storage ofthe image data in the temporary storage means under control of the imageinput control step and, when a predetermined unit storage amount of datahas been stored, generating storage information indicating this; acoding step of reading the image data stored in the temporary storagemeans to subject the image data to a predetermined coding process and,when a predetermined unit processing amount of data has been subjectedto the coding process, generating process information indicating this;and a control information generating step of generating first controlinformation used in said image input control step to control thestorage, and second control information used in said coding step tocontrol the coding process, according to the storage informationgenerated in said storage control step and the process informationgenerated in said coding step.
 7. An image processing method as definedin claim 6, wherein, in said control information generating step,storage stop information indicating that the storage of the input imagedata should be stopped is generated as the first control information,and coding stop information indicating that the coding process should bestopped is generated as the second control information.
 8. An imageprocessing method as defined in claim 6, wherein, in said controlinformation generating step, storage stop information indicating thatthe storage of the input image data should be stopped is generated asthe first control information, and continuous process informationindicating how many times the coding process on the unit processingamount of image data can be continuously performed in said coding stepis generated as the second control information.
 9. An image processingmethod as defined in claim 6, wherein said control informationgenerating step comprises: a storage information counting step ofcounting the storage information and holding the result as a storageinformation count value; a process information counting step of countingthe process information and holding the result as a process informationcount value; an addition control step of outputting an addition enablingsignal when the count of the storage information is performed apredetermined number of times, and outputting an addition disablingsignal when the count of the process information is performed apredetermined number of times; a storage information count value changestep of adding a predetermined value to the storage information countvalue according to the addition enabling signal or the additiondisabling signal, thereby generating a storage information count valueafter processing; a codable unit number generating step of subtractingthe process information count value from the storage information countvalue after processing, thereby generating a codable unit number; afirst control information generating step of comparing the codable unitnumber with a first predetermined value and, when these values match,generating the first control information; and a second controlinformation generating step of comparing the codable unit number with asecond predetermined value and, when these values match, generating thesecond control information.
 10. An image processing method as defined inclaim 6, wherein said control information generating step comprises: astorage information counting step of counting the storage informationand holding the result as a storage information count value; a processinformation counting step of counting the process information andholding the result as a process information count value; an additioncontrol step of outputting an addition enabling signal when the count ofthe storage information is performed a predetermined number of times,and outputting an addition disabling signal when the count of theprocess information is performed a predetermined number of times; astorage information count value change step of adding a predeterminedvalue to the storage information count value according to the additionenabling signal or the addition disabling signal, thereby generating astorage information count value after processing; a codable unit numbergenerating step of subtracting the process information count value fromthe storage information count value after processing, thereby generatinga codable unit number; a first control information generating step ofcomparing the codable unit number with a first predetermined value and,when these values match, generating the first control information; and asecond control information generating step in which the codable unitnumber is used as the second control information.
 11. An imageprocessing apparatus for storing input image data and subjecting thestored image data to a coding process, said image processing apparatuscomprising: a temporary storage device operable to store the input imagedata; an image input control device operable to control storage of theinput image data in said temporary storage device; a storage controldevice operable to execute storage of the image data in said temporarystorage device under control of said image input control device and,when a predetermined unit storage amount of data has been stored,generate storage information indicating this; a coding device operableto read the image data stored in said temporary storage device tosubject the image data to a predetermined coding process and, when apredetermined unit processing amount of data has been subjected to thecoding process, generate process information indicating this; and acontrol information generating device operable to generate first controlinformation used by said image input control device to control thestorage, and generate second control information used by said codingdevice to control the coding process, in accordance with the storageinformation generated by said storage control device and the processinformation generated by said coding device.
 12. An image processingapparatus as defined in claim 11, wherein said control informationgenerating device is operable to generate, as the first controlinformation, storage stop information indicating that the storage of theinput image data should be stopped, and generate, as the second controlinformation, coding stop information indicating that the coding processshould be stopped.
 13. An image processing apparatus as defined in claim11, wherein said control information generating device is operable togenerate, as the first control information, storage stop informationindicating that the storage of the input image data should be stopped,and generate, as the second control information, continuous processinformation indicating how many times said coding device cancontinuously perform the coding process on the unit processing amount ofimage data.
 14. An image processing apparatus as defined in claim 11,wherein said control information generating device comprises: a storageinformation counting device operable to count the storage informationand hold the result as a storage information count value; a processinformation counting device operable to count the process informationand hold the result of the count as a process information count value;an addition control device operable to output an addition enablingsignal when the count of the storage information is performed apredetermined number of times, and output an addition disabling signalwhen the count of the process information is performed a predeterminednumber of times; a storage information count value change deviceoperable to add a predetermined value to the storage information countvalue according to the addition enabling signal or the additiondisabling signal, thereby generating a storage information count valueafter processing; a codable unit number generating device operable tosubtract the process information count value from the storageinformation count value after processing, thereby generating a codableunit number; a first control information generating device operable tocompare the codable unit number with a first predetermined value and,when these values match, generate the first control information; and asecond control information generating device operable to compare thecodable unit number with a second predetermined value and, when thesevalues match, generate the second control information.
 15. An imageprocessing apparatus as defined in claim 11, wherein said controlinformation generating device comprises: a storage information countingdevice operable to count the storage information and hold the result asa storage information count value; a process information counting deviceoperable to count the process information and hold the result as aprocess information count value; an addition control device operable tooutput an addition enabling signal when the count of the storageinformation has been performed a predetermined number of times, andoutput an addition disabling signal when the count of the processinformation has been performed a predetermined number of times; astorage information count value change device operable to add apredetermined value to the storage information count value according tothe addition enabling signal or the addition disabling signal, therebygenerating a storage information count value after processing; a codableunit number generating device operable to subtract the processinformation count value from the storage information count value afterprocessing, thereby generating a codable unit number; and a firstcontrol information generating device operable to compare the codableunit number with a first predetermined value and, when these valuesmatch, generate the first control information; wherein the codable unitnumber is used as the second control information.
 16. An imageprocessing method for storing input image data in a temporary storagedevice, and subjecting the stored image data to a coding process, saidimage processing method comprising: controlling storage of the inputimage data in the temporary storage device; executing storage of theimage data in the temporary storage device under control of saidcontrolling and, when a predetermined unit storage amount of data hasbeen stored, generating storage information indicating this; reading theimage data stored in the temporary storage device to subject the imagedata to a predetermined coding process and, when a predetermined unitprocessing amount of data has been subjected to the coding process,generating process information indicating this; and generating firstcontrol information used in said controlling to control the storage, andsecond control information used in said reading to control the codingprocess, according to the storage information generated in saidexecuting storage and the process information generated in said reading.17. An image processing method as defined in claim 16, wherein, in saidgenerating, storage stop information indicating that the storage of theinput image data should be stopped is generated as the first controlinformation, and coding stop information indicating that the codingprocess should be stopped is generated as the second controlinformation.
 18. An image processing method as defined in claim 16,wherein, in said generating, storage stop information indicating thatthe storage of the input image data should be stopped is generated asthe first control information, and continuous process informationindicating how many times the coding process on the unit processingamount of image data can be continuously performed in said reading isgenerated as the second control information.
 19. An image processingmethod as defined in claim 16, wherein said generating comprises:counting the storage information and holding the result as a storageinformation count value; counting the process information and holdingthe result as a process information count value; outputting an additionenabling signal when the count of the storage information is performed apredetermined number of times, and outputting an addition disablingsignal when the count of the process information is performed apredetermined number of times; adding a predetermined value to thestorage information count value according to the addition enablingsignal or the addition disabling signal, thereby generating a storageinformation count value after processing; subtracting the processinformation count value from the storage information count value afterprocessing, thereby generating a codable unit number; comparing thecodable unit number with a first predetermined value and, when thesevalues match, generating the first control information; and comparingthe codable unit number with a second predetermined value and, whenthese values match, generating the second control information.
 20. Animage processing method as defined in claim 16, wherein said generatingcomprises: counting the storage information and holding the result as astorage information count value; counting the process information andholding the result as a process information count value, outputting anaddition enabling signal when the count of the storage information isperformed a predetermined number of times, and outputting an additiondisabling signal when the count of the process information is performeda predetermined number of times; adding a predetermined value to thestorage information count value according to the addition enablingsignal or the addition disabling signal, thereby generating a storageinformation count value after processing; subtracting the processinformation count value from the storage information count value afterprocessing, thereby generating a codable unit number; comparing thecodable unit number with a first predetermined value and, when thesevalues match, generating the first control information; and using thecodable unit number as the second control information.
 21. An imageprocessing apparatus as defined in claim 1, wherein the predeterminedunit storage amount of data and the predetermined unit processing amountof data each comprise one slice unit quantity of data.
 22. An imageprocessing method as defined in claim 6, wherein the predetermined unitstorage amount of data and the predetermined unit processing amount ofdata each comprise one slice unit quantity of data.
 23. An imageprocessing apparatus as defined in claim 11, wherein the predeterminedunit storage amount of data and the predetermined unit processing amountof data each comprise one slice unit quantity of data.
 24. An imageprocessing method as defined in claim 16, wherein the predetermined unitstorage amount of data and the predetermined unit processing amount ofdata each comprise one slice unit quantity of data.